A PLL is a well-known frequency-selective feedback system which is adapted to generate a signal which can synchronize with a reference input signal and closely track the frequency changes which may be associated with the input signal. PLLs are utilized in numerous applications, including communication, telemetry and data-recovery applications.
The range of frequencies over which the PLL can maintain synchronization with an input signal is typically defined as the tracking range, or lock range, of the system. This is different from the range of frequencies over which the PLL can first synchronize with the incoming signal, the latter range of frequencies being typically known as the capture range, or acquisition range, of the PLL. The capture range is characteristically always smaller than the tracking range in practical PLL circuits. Generally, the larger the tracking range of the PLL, the worse is the performance of the PLL. Ideally, a narrow tracking range is desirable in order to rapidly capture the input signal and to hold the frequency of the input signal more precisely while in lock. However, a narrow tracking range does not allow the PLL to maintain synchronization with the incoming signal over fluctuations in the frequency of the incoming signal, in addition to variations in operating conditions and/or manufacturing characteristics to which the PLL may be subjected, such as, for example, process, voltage supply and/or temperature (PVT).
In a satellite digital audio radio service (SDARS) application, a costly temperature compensated crystal oscillator (TCXO) is often employed to reduce the amount of frequency offset in the SDARS receiver. A high cost TCXO will typically exhibit a frequency offset variation of about ±15 ppm (parts per million) over a temperature range from about −40 to about 105 degrees Celsius. By comparison, a lower cost crystal may exhibit a frequency offset variation of about ±55 ppm over the same temperature range. About ±20 ppm to about ±35 ppm of the total frequency offset variation in the lower cost crystal can be attributed to temperature change, while the remaining frequency offset variation may be due to a number of other factors, including, for example, manufacturing variations, aging, and variations in board components (e.g., loading capacitor) which affect a loading impedance of the crystal. While it would be desirable to utilize a lower cost crystal in order to reduce the overall cost of the SDARS receiver, the frequency offset variation of the lower cost crystal is too large to satisfy the stringent frequency tracking requirements of many applications, such as SDARS.
Accordingly, there exists a need for an improved PLL which does not suffer from one or more of the above-noted problems exhibited by conventional PLLs.